Posts by Steve Bergman

21) Message boards : Number crunching : Effect of L2 cache size and FSB on models? (Message 34571) Posted 9 Aug 2008 by Steve Bergman Post: Apologies for posting this thread which is nearly identical to another recent thread in the forum. I searched for L2 and FSB before I posted and found nothing. But when I do a search for L2 now, I see this thread... but not this one (which clearly has L2 in the subject and also in the body): http://climateapps2.oucs.ox.ac.uk/cpdnboinc/forum_thread.php?id=6220
22) Message boards : Number crunching : Effect of L2 cache size and FSB on models? (Message 34570) Posted 8 Aug 2008 by Steve Bergman Post: First of all, hello. This is my first post here, and I\'ve just been running my first model for a couple of days. It\'s a HADCM. And I did reel a bit upon the realization of just how big a work unit actually is! But I understand why that must be. As tightly bound to that each element in the simulation is to all the other elements, its not like anything can be broken up into smaller pieces. The simulation must be able to quickly interrelate vast quantities of data for each time step. Which brings me to my actual question. To make it a little more concrete, let me say that I am running a Core 2 Duo E2140, and have just ordered a Core 2 Duo E7200. The E7200: 1. Runs a 58% higher clock, internally 2. Has 3 times the L2 cache. (3M vs 1M) 3. Runs a 33% faster FSB. (1066 vs 800) It seems to me that these large models probably access huge amounts of data for each time step. So the additional cache, memory bandwidth, and reduced memory latency should be pretty significant. Is that true? I have compared some of the values for those processors from the cpdn user machine pages, and it looks like those synthetic benchmarks show about a 55% higher integer performance and a 70% higher floating point for the E7200. (I\'m guessing that it is the floating point performance which dominates for cpdn.) However, I suspect that the benchmarks don\'t really concern themselves with the effects of memory bandwidth and latency. Hopefully, I will receive the new processor Monday and will be able to tell for sure. I\'m hoping that it will cut the 4.5 month ETA for this model down to about half that. Any thoughts would be welcome. Thanks, Steve Bergman

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